1. Field of the Invention
The present invention relates in general to phase difference detector circuits, particularly of the type employed in Phase-Locked Loop (PLL) circuits.
2. Description of the Related Art
PLL circuits are largely exploited in several different applications; for instance, in the field of telecommunications, PLL circuits are used for realizing frequency synthesizers.
As known, the PLL is a circuit with negative feedback that allows obtaining, starting from a reference signal having a given frequency, or reference frequency, a signal having frequency equal to the reference frequency multiplied by a prescribed multiplication factor.
More particularly, a PLL circuit includes an phase difference detector adapted to detect the phase difference between the reference signal and a feedback signal, derived from the output signal of the PLL circuit through a feedback network comprising a frequency divider; the division factor implemented by the frequency divider corresponds to the aforesaid multiplication factor. The phase difference detector, typically constituted by a phase and frequency detector followed by a charge pump circuit, produces a signal, for instance a current signal, proportional to the detected phase difference. Such signal, filtered by a loop filter with transfer function such as to eliminate the high frequency components, for example a signal that is integrated and converted into a voltage signal, constitutes the control signal of a voltage controlled oscillator, that generates the output signal of the PLL circuit.
The PLL circuit is capable of producing signals with frequency equal to a multiple of the frequency of the reference signal. Varying the multiplication factor, and thus the division factor of the frequency divider in feedback network, it is possible to generate signals of different frequencies, in the art referred to as “channels”.
PLL circuits are known in which the frequency multiplication factor N is an integer. The performances of these PLL circuits, denominated integer N PLL circuits, derive from a compromise in the choice of the design parameters, particularly as far as the bandwidth, the settling time, the distance (in frequency) between the different channels or resolution, the phase noise and the consumption are concerned.
These limitations are overcome by the so-called fractional N PLL circuits, that allow achieving non-integer multiplication factors of the reference frequency. Particularly, for a same distance between the different channels, the fractional N PLLs are characterized by a reduced phase noise compared to the integer N PLLs.
In order to obtain a fractional multiplication factor, given a generic channel, the division factor of the frequency divider in the feedback network is made to vary dynamically between two integer values, for instance two consecutive integer values N and N+1, with a given periodicity. This technique allows generating signals whose frequency is equal to non-integer multiples of the frequency of the reference signal.
One of the main disadvantages of the fractional N PLL circuits consists in the generation of spurious signals. Particularly, such spurious signals are generated in consequence of the periodic variation of the frequency division factor, from N to N+1. The spurious signals are found at frequencies differing from the reference frequency of multiples of the frequency with which the frequency division factor is made to vary.
A known technique for limiting the effect of the spurious signals consists in using a ΣΔ modulator for controlling the instantaneous frequency division factor of the frequency divider.
The level of the spurious signals is increased by the presence of inevitable nonlinearities in the PLL loop, and particularly in the phase difference detector. Particularly, the nonlinearities in the input-output characteristic of such subsystem of the PLL determines an increase in the level of the spurious signal situated at the fractional frequency equal to the product of the reference frequency for the selected channel divided by the overall number of channels. The level of such spurious signal is particularly high for that channels that are characterized by a fractional frequency lower than the loop bandwidth, because of the limited filtering band of the loop filter.
In B. De Muer et al., “A CMOS Monolithic ΣΔ-Controlled Fractional-N Frequency Synthesizer for DCS-1800”, IEEE JSSC, No. 7, July 2002, pages 835 to 844, it is underlined that the nonlinearities in the input-output characteristic of the phase difference detector are the main cause of spurious signals, and thus an optimization of the phase and frequency detector and of the charge pump circuit is desirable. Particularly, the authors of such article indicates two types of nonlinearity: a dead zone present in the input-output characteristic for small phase difference values, and a different gain for positive and negative phase differences, consequence of the mismatches in the current generators that serve to generate the current signal proportional to the phase difference.
The Applicant has observed that eliminating the two aforementioned types of nonlinearity does not allow reducing enough the level of the spurious signals.